サぺルEnglish · 5 months agoHow to Program an Altera CPLD Logic Chip From 1998 that's in JTAG LOCKOUT ? [#61]plus-squarewww.youtube.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkHow to Program an Altera CPLD Logic Chip From 1998 that's in JTAG LOCKOUT ? [#61]plus-squarewww.youtube.comサぺルEnglish · 5 months agomessage-square0linkfedilink
サぺルEnglish · 1 year agoGetting Started with W65C832plus-squarejoedavisson.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkGetting Started with W65C832plus-squarejoedavisson.comサぺルEnglish · 1 year agomessage-square0linkfedilink
サぺルEnglish · 1 year agoLattice Ice40, shift register debugger and some softwareplus-squarewww.youtube.comexternal-linkmessage-square1linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkLattice Ice40, shift register debugger and some softwareplus-squarewww.youtube.comサぺルEnglish · 1 year agomessage-square1linkfedilink
サぺルEnglish · 2 years agoA minimal GPU design in Verilog to learn how GPUs work from the ground upplus-squaregithub.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkA minimal GPU design in Verilog to learn how GPUs work from the ground upplus-squaregithub.comサぺルEnglish · 2 years agomessage-square0linkfedilink
サぺルEnglish · 3 years agoHDMI ISA graphics card for vintage PCs by improving the Graphics Gremlinplus-squareyeokhengmeng.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkHDMI ISA graphics card for vintage PCs by improving the Graphics Gremlinplus-squareyeokhengmeng.comサぺルEnglish · 3 years agomessage-square0linkfedilink
サぺルEnglish · 3 years agoOn the Origin of Circuitsplus-squarewww.damninteresting.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkOn the Origin of Circuitsplus-squarewww.damninteresting.comサぺルEnglish · 3 years agomessage-square0linkfedilink
サぺルEnglish · 3 years agoA Single-Cycle 64-Bit RISC-V Register Fileplus-squaredanielmangum.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkA Single-Cycle 64-Bit RISC-V Register Fileplus-squaredanielmangum.comサぺルEnglish · 3 years agomessage-square0linkfedilink
サぺルEnglish · edit-23 years agoVIC II-kawari: Commodore 64 VIC-II 6567/6569 Replacement Projectplus-squaregithub.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkVIC II-kawari: Commodore 64 VIC-II 6567/6569 Replacement Projectplus-squaregithub.comサぺルEnglish · edit-23 years agomessage-square0linkfedilink
サぺルEnglish · edit-23 years agoGitHub - sylefeb/a5k: Another World on a chipplus-squaregithub.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkGitHub - sylefeb/a5k: Another World on a chipplus-squaregithub.comサぺルEnglish · edit-23 years agomessage-square0linkfedilink
サぺルEnglish · 3 years agoAn attempt to recreate the RP2040 PIO in an FPGAplus-squaregithub.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkAn attempt to recreate the RP2040 PIO in an FPGAplus-squaregithub.comサぺルEnglish · 3 years agomessage-square0linkfedilink
サぺル · 4 years agoGitHub - FPGAwars/icestudio: Visual editor for open FPGA boardsplus-squaregithub.comexternal-linkmessage-square2linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkGitHub - FPGAwars/icestudio: Visual editor for open FPGA boardsplus-squaregithub.comサぺル · 4 years agomessage-square2linkfedilink
サぺル · 4 years agoIntel announces new FPGA families - FPGA'erplus-squarefpgaer.techexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkIntel announces new FPGA families - FPGA'erplus-squarefpgaer.techサぺル · 4 years agomessage-square0linkfedilink
サぺル · 4 years agoProject F: FPGA Devplus-squareprojectf.ioexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkProject F: FPGA Devplus-squareprojectf.ioサぺル · 4 years agomessage-square0linkfedilink
サぺル · 4 years agoNokia zaprasza na FPGA Hackathon do Krakowaplus-squarefpgahackathon.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkNokia zaprasza na FPGA Hackathon do Krakowaplus-squarefpgahackathon.comサぺル · 4 years agomessage-square0linkfedilink
naurM · 4 years agoLightning Talk: Creating a GPU With C++ and an FPGA - Iwan Smith - CppCon 2021plus-squarewww.youtube.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkLightning Talk: Creating a GPU With C++ and an FPGA - Iwan Smith - CppCon 2021plus-squarewww.youtube.comnaurM · 4 years agomessage-square0linkfedilink
lemmyMA · 4 years agoSuperRTplus-squarewww.shironekolabs.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkSuperRTplus-squarewww.shironekolabs.comlemmyMA · 4 years agomessage-square0linkfedilink
naurM · 4 years agoVerilog, Formal Verification and Verilator Beginner's Tutorialplus-squarezipcpu.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkVerilog, Formal Verification and Verilator Beginner's Tutorialplus-squarezipcpu.comnaurM · 4 years agomessage-square0linkfedilink
